Dual-stress liner technology is a known strained silicon process which enhances the performance of n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs), by stretching the bonds between silicon atoms in one type of transistor and compressing them in the other. To create a dual-stress liner, a highly tensile Si3N4 liner is deposited over a semiconductor device that includes one or more pFETs and nFETs. The film is then patterned and etched from pFET regions. Next, a highly compressive Si3N4 liner is deposited, and this film is then patterned and etched from nFET regions.
Dual-stress liner technology is known to improve performance of both nFETs and pFETs. However, two stress liner materials are required for nFETs and pFETs, respectively. In order to avoid moisture or mobile ions from entering the FETs during the back end of line (BEOL) process, it is important that the two liner materials do not have any voids or seams between them. This means the two liner materials need to overlap.
After the liner films are applied, the plugs of contact structures are added by etching holes in the liner materials at the desired locations and then filling the holes with the desired metal to form the plugs.
However, when determining placement of the contact structure (which includes both a plug and contact), some contact structures need to be placed close to, or even directly on, the overlap region in the chip. Since the liner thickness in an overlap region is twice as thick as in a non-overlap region, it can be difficult to simultaneously etch the contact holes in both the overlap regions and the non-overlap regions without resulting in under-etching or over-etching in some contact holes. Under-etching results open an unintended open circuit, and over-etching can destroy the device or at least significantly reduce performance.
Moreover, by nature of the etching process, the hole formed for the plugs has sides that taper inwardly so that the resulting plugs are smaller at the bottom than at the top. That is, a tapered plug forms with a bottom inner taper angle of greater than 90 degrees. The smaller the contact area between the bottom of the plug and the silicon layer, the larger the resistance of that contact area. It is generally preferred that the contact resistance between a plug and the circuit element being serviced by that plug be as small as possible. A higher contact resistance reduces performance and increases power consumption.
For example, as shown in FIG. 1, nFET 2 and pFET 3 are formed on a silicon layer 1. A dummy gate or poly-interconnect 4 is formed between the nFET 2 and the pFET 3. A first silicon nitride layer 5 (tensile stress liner) is applied to the silicon layer and a portion of the first silicon nitride layer is removed. A second silicon nitride layer 6 (compressive stress liner) is applied to the silicon layer and a portion of the second silicon nitride layer is removed. Plugs 7a and 7b are then added by etching holes in the silicon nitride layers and filling the holes. The etching for the plugs is typically conducted simultaneously across the entire semiconductor wafer.
Because the thickness of the silicon nitride is uneven, portions of the silicon nitride may be over-etched or under-etched. For example, in FIG. 1, the overlap of the tensile stress liner 5 and the compressive stress liner 6 causes under-etching in the overlap region. Under-etching, for example, results in plug 7b not contacting silicon layer 1, providing a gap or open area that affects the performance of pFET 3.